1. Field of the Invention
The present invention relates to a processing apparatus having a constant current circuit.
2. Related Background Art
FIG. 5 is a circuit diagram of a conventional MOS solid-state image pickup element. FIG. 6 is a timing chart of this element.
Referring to FIG. 5, each photoelectric conversion cell S is comprised of a photodiode 1 (1-1-1, 1-1-2, 1-1-3, . . . ), transfer switch 2 (2-1-1, 2-1-2, 2-1-3, . . . ), reset switch 3 (3-1-1, 3-1-2, 3-1-3, . . . ), amplification transistor 4 (4-1-1, 4-1-2, 4-1-3, . . . ), and selection switch 5 (5-1-1, 5-1-2, 5-1-3, . . . ). As the transfer switch 2, reset switch 3, amplification transistor 4, and selection switch 5, MOS transistors can be used.
The signal stored in the photodiode 1 arranged in each photoelectric conversion cell S is read by the amplification transistor 4 as a voltage to a vertical output line 8 (8-1, 8-2, 8-3, . . . ) connected to the amplification transistor 4. At this time, since a source follower circuit is constituted by the amplification transistor 4 and a load transistor 9 (9-1, 9-2, . . . ) serving as a constant current circuit, a voltage signal corresponding to the signal in the photodiode 1 is read to the vertical output line 8. Voltages are applied to the gates of the load transistors 9-1, 9-2, 9-3, . . . by a constant current source 25 and transistors 26 whose drains are short-circuited to the gates, thereby forming current mirror circuits. The load transistor 9, constant current source 25, and transistor 26 constitute a constant current supply means.
This arrangement also includes a source follower circuit which receives a voltage from the vertical output line 8 to drive a clamp capacitor 13 (13-1, 13-2, 13-3, . . . ). This source follower circuit is comprised of a transistor 11 (11-1, 11-2, 11-3, . . . ) and a transistor 12 (12-1, 12-2, 12-3, . . . ) serving as a constant current circuit. Voltages are applied to the gates of the transistors 12-1, 12-2, 12-3, . . . by a constant current source 24 and transistors 23 whose drains are short-circuited to the gates, thereby forming current mirror circuits. A transistor 14 (14-1, 14-2, 14-3, . . . ) serves to set a predetermined potential at the output-side terminal of the clamp capacitor 13. A power supply terminal 22 is set at a predetermined potential.
A signal voltage appearing on the vertical output line 8 passes through the transistor 11 serving as a buffer amplifier, the clamp capacitor 13, a vertical signal line 16 (16-1, 16-2, 16-3, . . . ), a horizontal transfer switch 17 (17-1, 17-2, 17-3, . . . ), and a horizontal signal line 18. The voltage signal is then output from an output terminal 21 through an amplifier 20 and negative feedback capacitor 19. The transistor 12, a transistor 23, and the constant current source 24 constitute a constant current supply means.
The horizontal transfer switches 17 are sequentially selected by the horizontal shift register to sequentially output signals from the vertical signal line 16 to the horizontal signal line 18. The control terminals (corresponding to the gates of MOS transistors) of the transfer switches 2 (2-1-1, 2-1-2, . . . , 2-2-1, 2-2-2, . . . ) of the respective cells arranged in the row direction are connected to signal lines 7 (7-1, 7-2, . . . ). The control terminals of the reset switches 3 (3-1-1, 3-1-2, . . . , 3-2-1, 3-2-2, . . . ) of the respective cells arranged in the row direction are connected to signal lines 6 (6-1, 6-2, . . . ). The control terminals of the selection switches 5 (5-1-1, 5-1-2, . . . , 5-2-1, 5-2-2, . . . ) of the respective cells arranged in the row direction are connected to signal lines 10 (10-1, 10-2, . . . ).
The operation of the above MOS solid-state image pickup element will be described with reference to FIG. 6. FIG. 6 is a timing chart showing the operation of a clamp noise reduction circuit for reading a signal and reducing noise in the signal in the MOS solid-state image pickup element.
As shown in FIG. 6, an H-level signal pulse 101 is applied to the signal line 10-1 to activate the amplification transistors 4-1-1, 4-1-2, . . . on the first row. An H-level signal pulse 102 is applied to the signal line 6-1 to turn on the reset transistors 3-1-1, 3-1-2, . . . on the first row to make a reset potential for the sensor appear on the vertical output lines 8-1, 8-2, 8-3, . . . . At almost the same time, an H-level signal pulse 104 is applied to the gates of the clamp transistors 14-1, 14-2, 14-3, . . . to apply, across the two terminals of each of the clamp capacitors 13-1, 13-2, 13-3, . . . , output voltages from the source followers 11-1, 11-2, and 11-3 in accordance with the potential of the clamp reference voltage applied from the terminal 22 and the sensor reset potential. With this operation, noise signals are read from the respective cells arranged on the first row to the vertical output line 8, thereby clamping the noise signals in the clamp capacitors 13.
An H-level signal pulse 103 is then applied to the signal line 7-1 to turn on the transfer switches 2-1-1, 2-1-2, 2-1-3, . . . . As a consequence, signal outputs corresponding to the signal charges in the photodiodes 1-1-1, 1-1-2, 1-1-3, . . . are read to the vertical output lines 8-1, 8-2, 8-3, . . . . Along with this operation, a potential corresponding to the output of the source follower 11 appears at one terminal of the clamp capacitor 13.
Subsequently, H-level signal pulses 105, 106, and 107 are sequentially applied to the gates of the horizontal transfer switches 17-1, 17-2, 17-3, . . . to sequentially turn on the horizontal transfer switches 17-1, 17-2, 17-3, . . . . As a consequence, a signal from each cell on the first row is output to the horizontal signal line 18. The signal charge is then converted into a signal voltage by the amplifier 20 and negative feedback capacitor 19 and output from the output terminal 21.
The above-described operation is performed with respect to the respective cells arranged on the second row, third row, . . . to read signals from all the cells.
The constant current circuit for the source follower in the above-described arrangement is formed on the premise that the gate and source of the transistor of the constant current circuit are set at the same potential (GND potential in this case). In practice, aluminum interconnections formed on a semiconductor substrate have certain resistances, and hence a voltage drop occurs when a current flows through such an interconnection. As the chip size of a sensor IC having many pixels increases, the length of an aluminum interconnection forming a GND line increases. As a consequence, an increase in the above voltage drop cannot be neglected. The set current of the constant current circuit for the source follower connected to each vertical output line 8 in FIG. 5 varies, and the current values decreases with increase of the distance from the GND terminal of the IC, resulting in a certain gradient (shading) in the output voltage of each vertical signal line. In addition, when the sensor is to be driven at high speed, the output impedance of the source follower must be decreased. Hence, the set current of the constant current circuit connected to the above source follower must be increased. As a result, the voltage drop at the GND interconnection increases, and hence the current value of the constant current greatly varies.
FIGS. 7A and 7B are a circuit diagram and graph schematically showing the above problem. Referring to FIG. 7A, this arrangement includes a power supply terminal 41, a GND terminal 42, a reference constant current source 43, vertical output lines 44 (44-1, 44-2, . . . ) respectively corresponding to the vertical output lines 8-1, 8-2, . . . in FIG. 5, and output terminals 45 of source followers. Transistors 46 and 47 constitute a source follower circuit. The GND interconnections have parasitic resistors 48 (48-1, 48-2, . . . ).
As shown in the graph of FIG. 7B, the current of the constant current circuit for each source follower decreases with an increase in distance from the GND terminal 42 with respect to the current of the reference current source.